In many designs, power consumption has become a key parameter. In high performance designs, excessive power dissipation beyond the critical point temperature can degrade reliability. On the chip, the voltage drops, and since the on-chip logic is no longer operating under ideal voltage conditions, power consumption can even affect timing. To handle power consumption issues, designers must build power-sensitive methodologies throughout the chip design process to handle power. You shouldn't wait until you are out of the tape to start worrying about power consumption. If so, you may find that the work of reducing power consumption is done too little and too late.

Ignore any factor that consumes power. For example, when you try to reduce switching power consumption, leakage power may be a more important part. Excessive peak power consumption can cause large noise spurs on-chip and off-chip.

It is believed that reducing the supply voltage or using a small geometry process will solve the power problem. Lower supply voltages reduce noise margins and slow down circuit operation, making it difficult to achieve timing closure or even to meet functional specifications. At 90 nm and below, there will be greater leakage current.

Count on a "button-like" low-power solution or method. Power management must be implemented at all stages of the design process—sometimes design decisions are needed, and sometimes more automated.

Power-sensitive designs and automatic power reduction are considered mutually exclusive. If you combine the two in a complete power management design approach, these two technologies will effectively help you overcome power challenges.

Interconnects are beginning to dominate switch power consumption, just as the first few process nodes dominate timing. The image to the right shows the relative impact of the interconnect on total dynamic power consumption. Today, designers have the ability to reduce power consumption through wiring optimization.

In the physical design phase, designers can also find more opportunities to automatically reduce consumption. Automatic consumption reduction during the physical design process will complement the early stages of the design process and the reduction in power consumption during the logic synthesis process.

Power consumption is an “opportunity equal opportunity”: from early design trade-offs to automatic physical power optimization, all power-reduction technologies complement each other and need to be considered as part of every modern design flow. Engineers can apply the following criteria as an integral part of any design methodology when solving power consumption problems.

It should be understood that power consumption is a design parameter that is as important as performance (timing), functionality, and your design cost. Take power factor into account when making design decisions and trade-offs. Early and sensible design decisions in the process can result in substantial power savings. However, it is more difficult to automatically reduce power consumption during the initial stages of the design process.

Advanced design techniques are employed to reduce power consumption, such as voltage/power island division, block-level clock gating, power down mode, efficient memory configuration, and parallelism. Advanced abstraction techniques that reduce power consumption include dynamic voltage and frequency scaling, memory subsystem partitioning, voltage/power island partitioning, and software-driven sleep modes.

Accurately estimate power consumption at the RTL and quasi RTL levels. It is the designer's task to understand the design factors and specifications that have an impact on overall power consumption, but it is helpful for designers to provide advanced power estimation tools that provide designers with the information they need to make appropriate tradeoffs.

Study all the opportunities to automatically reduce power consumption, while reducing power consumption without affecting timing or increasing area. For example, during the logic synthesis phase, register clock gating can be used effectively, but doing so can cause timing and signal integrity issues in the physical design process. An alternative approach is to implement clock gating during the physical design phase, which provides accurate timing and signal integrity information.

Power is saved by optimizing the interconnect during the physical design phase to reduce the capacitance of high-power nodes. Once the interconnect capacitance is reduced, the logic gates that drive these lower capacitive loads can be smaller or optimized to produce lower power consumption. The use of multiple threshold voltage cell replacement to reduce leakage power can also be effectively implemented at the physical level.

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